The present invention relates to a voltage adder circuit. A conventional voltage adder circuit, as shown in FIG. 1, employs a parallel feedback path around an operational amplifier A. More specifically, input terminals IN.sub.1, IN.sub.2 and IN.sub.3 are connected through corresponding resistors R.sub.1, R.sub.2 and R.sub.3 to an inverting input terminal of the amplifier A. Parallel negative feedback from an output terminal OUT is provided through a resistor R.sub.4. In the circuit of FIG. 1, the output voltage V.sub.o is: EQU V.sub.o =R.sub.4 (V.sub.i1 /R.sub.1 +V.sub.i2 /R.sub.2 +V.sub.i3 /R.sub.3). [1]
This circuit forms an adder for V.sub.i1, V.sub.i2 and V.sub.i3. However, this circuit cannot be used in the case where all the inputs V.sub.i1, V.sub.i2 and V.sub.i3 are supplied in balanced form where the levels may float with respect to the ground level.
In view of this drawback, it is an object of the invention to provide a voltage adder circuit which functions as an adder even for balanced inputs which float with respect to ground level.